The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 05, 1999
Filed:
Jul. 16, 1997
Ian Victor Devereux, Cherry Hinton, GB;
Nicholas Andrew Salter, Cherry Hinton, GB;
Arm Limited, Cambridge, GB;
Abstract
The present invention provides a data processing apparatus for fetching an instruction in to an instruction cache, comprising an instruction cache for storing instructions, and a processor core for outputting an instruction address to the instruction cache on an instruction address bus, and for receiving the instruction corresponding to that instruction address on an instruction data bus The processor core is arranged to issue a predetermined control signal to the instruction cache when outputting the instruction address to cause the instruction cache to perform an instruction fetch procedure. In accordance with the present invention, a coprocessor is provided for executing a first predetermined instruction also executed by the processor core, the first predetermined instruction causing the coprocessor to issue the predetermined control signal to the instruction cache, and causing the processor core to output to the instruction cache the instruction address data for an instruction to be added to the instruction cache without issuing the predetermined control signal. Further, the instruction cache is responsive to the predetermined control signal from the coprocessor and the instruction address from the processor core to perform the instruction fetch procedure, and, if this results in a cache miss, to cause the retrieval of the instruction from memory for storage in the instruction cache, the processor core being arranged to ignore the retrieved instruction. The above approach allows an instruction to be pre-fetched and stored in the instruction cache without that instruction being returned to the processor core for execution, and without any additional logic needing to be added to the instruction cache to support pre-fetching.