Asynchronous memory interface for a video processor with a 2.sup.n sized

Abstract

A memory controller for a special purpose digital video processor. To achieve a speed enhancement when using multiple bank memory such as SDRAM, the memory controller arbitrates requests for access to the memory such that, if possible, sequential memory accesses are directed to alternating memory banks. To facilitate access to contiguous blocks of memory such as are often accessed in video signal processing, the memory controller includes an address generator for generating multiple memory addresses in response to a single memory access request. The memory controller further includes features which permit the use of multiple physical memory configurations. Specifically, the memory controller includes a memory address mapper for translating virtual memory address signals into physical memory address signals for address memory; for different memory configurations, the translation is different. To further optimize the use of different memory chips, an asynchronous clock is used by the memory relative to the clock of the special purpose processor. Data passing to or from the memory is synchronized to the memory or processor clock by a special purpose data buffer/synchronizer of size 2.sup.N. The data buffer/synchronize also uses N+1 bit wide gray coded counters. Also, the memory controller includes a programmable memory interface for generating column address strobe (CAS) and row address strobe (RAS) signals in accordance with the timing specification of the specific memory configuration in use.