The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 28, 1999
Filed:
Apr. 17, 1998
Jerome Bombal, Nice, FR;
Laurent Souef, Mouans Sartoux, FR;
VLSI Technology, Inc., San Jose, CA (US);
Abstract
A low power scannable asynchronous counter which is fully testable and which consumes low power in a functional mode consists of counter cells cascaded through NOR gate circuits to which clock signals are applied for each of the stages or cells. Each of the stages or cells comprises a flip-flop and a multiplexer which together operate as a toggle flip-flop only when all of the previous flip-flops are set. The result is that the flip-flop clock is forced high preventing any transition of the flip-flop internal clock tree for all stages or cells where the output is low. Thus, no power consumption of such stages takes place during functional operation. In the scan test mode, the counter operates as a shift register and it is fully testable.