The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 28, 1999

Filed:

Sep. 29, 1995
Applicant:
Inventors:

Manickam R Sridhar, Holliston, MA (US);

Neil Sheer, Foxboro, MA (US);

Assignee:

Motorola Inc., Schaumburg, IL (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04B / ; H04L / ;
U.S. Cl.
CPC ...
375219 ; 375222 ;
Abstract

An apparatus (200) and method for load balancing for a processor (103) operable in data terminal equipment (102), such as a personal computer or workstation, for operation of a data communications program for data transmission and reception over a communications channel (105), concurrently with the operation of other applications programs. The apparatus includes a loading selector (205) coupleable to a user interface (100) for selection of a data transfer priority. A priority translator (210) coupled to the load selector (205) maps or translates the data transfer priority to a modulation mode or to a subset of modulation modes. The priority translator (210) may also determine processor availability, which is then also mapped to a modulation mode or to a subset of modulation modes. A modulation mode controller (215) coupled to the priority translator (210) then limits or overrides automode functions or operations during a training period of the data communications devices for data transfer, limiting the modulation mode to one within the subset of modulation modes. Depending upon the data transfer priority selected by the user, the processor (103) has sufficient remaining availability for the concurrent and effective operation of other applications programs.


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