The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 28, 1999
Filed:
Dec. 17, 1996
Tokuya Osawa, Tokyo, JP;
Hideshi Maeno, Tokyo, JP;
Mitsubishi Denki Kabushiki Kaisha, Tokyo, JP;
Abstract
In a normal operation, a shift mode signal (SM) is set to '0' to propagate signals applied to '0'-input ends of selectors (10 to 12), i.e., outputs of a logic unit (80). In a logic scan test on logic units (80, 81), by setting a test-mode signal to '1', an ordinary scan test is performed with a scan path of simple configuration, having bits as much as write data and employing scan flip flops consisting of pairs of selectors (10 to 12) and flip flops (30 to 32) respectively. The flip flops used for writing in the normal operation can be also used as those used for the scan flip flops in the logic test. Thus, a configuration of the scan path to achieve excellent area-efficiency is provided.