Test method of integrated circuit devices by using a dual edge clock

Abstract

A test method can test high speed synchronous memory devices by using a tester having a minimum rate and a minimum clock cycle slower than operating speed of the devices to be tested. The test method transforms a pulse signal generated by the tester to be transformed into a clock signal having a frequency higher than the minimum rate, a test cycle of the test equipment then being determined based on a cycle time of the pulse signal, the operating cycle of the IC devices being determined based on a cycle time of the clock signal, and an input setup time and an input hold time of control signals which are supplied from the tester to the devices are separately measured for every two or more operating cycles of the IC devices.