The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 28, 1999

Filed:

Oct. 31, 1997
Applicant:
Inventor:

Robert L Payne, San Jose, CA (US);

Assignee:

VLSI Technology, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C / ;
U.S. Cl.
CPC ...
365200 ; 365 51 ; 365 63 ;
Abstract

Repair cells for performing metal-only functional repairs in a cell-based circuit layout design are described. The repair cells include a gate array under layer made-up of a group of uncommitted (not interconnected) transistors. A cluster of cells can be placed within the cell-based design in various locations and can be coupled together to form logic function elements. The repair cells can be added to cell-based designs during the metalization processing steps so as to repair/change the cell-based design's function. Furthermore, repair cells can be used as feedthrough cells to facilitate routing in the cell-based circuit layout. In this case, feedthrough cells having gate array underlayers may be arranged in columns or are placed in strategic spots within the layout to facilitate routing.


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