The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 28, 1999
Filed:
Dec. 29, 1997
K Nirmal Ratnakumar, San Jose, CA (US);
Cypress Semiconductor Corp., San Jose, CA (US);
Abstract
A counter-bias scheme to reduce or eliminate charge gain in a single-poly or double-poly electrically erasable (E.sup.2) cell having separate program and read transistors which may be configured as a 6-wire cell includes applying a counter-bias voltage to the drain of a program select transistor of the E.sup.2 cell during a read operation. The counter-bias voltage may be approximately equal to a voltage on the floating gate of the cell during the read operation. The present scheme reduces the threshold voltage shifts which may otherwise be experienced in the cell during continuous read operations. In particular, the counter-bias voltage acts to reduce the electric field across the tunnel oxide of the program select transistor, thus reducing the charge gain on the floating gate.