Digital signal transition edge alignment using interacting inverter

Abstract

Apparatus and method for aligning signal transition edges in high-speed complementary metal-oxide-semiconductor (CMOS) integrated circuits and other electronic circuits, systems and devices. A transition edge alignment circuit in accordance with the invention includes first and second inverter chains, each having a plurality of series-connected inverters. A first signal, which may be a digital logic signal, is applied to an input of the first inverter chain. A second signal, which may be a clock signal used to latch the logic signal in an integrated circuit, is applied to an input of the second inverter chain. The inverter chains may be constructed such that the inverters of the second chain have a stronger drive capability than the corresponding inverters of the first chain. Capacitive coupling is provided between outputs of inverters of the first chain and outputs of corresponding inverters of the second chain. The capacitive coupling provides interaction between the first and second inverter chains which acts to align transition edges of the first and second signals as the signals propagate through the respective first and second inverter chains. The edge alignment process may be facilitated by intentionally reducing a transition rate of either the first or second signal. This intentional transition rate reduction could be provided by applying the first or second signal to a delay circuit at an input of the corresponding inverter chain, or by connecting additional capacitive loads to outputs of the first several inverters in the corresponding inverter chain.