The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 28, 1999
Filed:
Nov. 28, 1997
John Rothgeb Fruth, Kokomo, IN (US);
Stephen Paul Barlow, Noblesville, IN (US);
Donald Ray Disney, Kokomo, IN (US);
Delco Electronics Corporation, Kokomo, IN (US);
Abstract
A semiconductor power device (100) that includes a number of bipolar or FET power devices (116), an over-voltage clamp (118), and an edge termination structure (110) that separates the power devices (116) and the over-voltage clamp (118). The power devices (116) are formed in an interior region (100a) of a semiconductor substrate (128), while the over-voltage clamp (118) is formed in a peripheral region (100b) of the substrate. The over-voltage clamp (118) and the gate/base terminals of the power devices (116) are formed in a polysilicon layer (126) overlying the substrate (128), such that the over-voltage clamp (118) is connected between the anode and gate/base terminals of each power device (116) to provide over-voltage protection. The edge termination structure (110) is formed in the substrate (128) so as to completely surround the interior region (100a) of the substrate (128), and therefore surrounds the power devices (116) to form a continuous barrier structure between the power devices (116) and the over-voltage clamp (118). The edge termination structure (110) includes a main junction (112) and at least one field-limiting ring (114), each of which is formed by a continuous well of the same electrical conductivity type. The edge termination structure (110) also includes a pair of field plates, a first (142) of which contacts the field-limiting ring (114) and a second (138) contacts the polysilicon layer (126) so as to make electrical contact with a gate terminal of the main junction (112).