Memory configuration cache with multilevel hierarchy least recently used

Abstract

A multilevel hierarchical least recently used cache replacement priority in a digital data processing system including plural memories, each memory connected to said system bus for memory access, a memory address generator generating addresses for read access to a corresponding of the memories and a memory cache having a plurality of cache entries, each cache entry including a range of addresses and a predetermined set of cache words. During each memory read the comparator compares the generated address with the address range of each cache entry. If there is a match, then the cache supplies a cache word corresponding to the least significant bits of the generated address from the matching cache entry. If there is no such match, the generated address is supplied to the memories and a set of words is recalled corresponding to the generated address. This set of words replaces a least recently used prior stored memory cache entry having the lowest priority level. The priority level for each cache entry may be recalled from a cache priority level look-up table or entered from an instruction via coding in opcode bits or a priority setting instruction. In an alternative embodiment this technique is used with a memory configuration cache storing memory access parameters for corresponding address ranges enabling adaption to plural memories requiring differing sets of memory access parameters.