The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 21, 1999

Filed:

Jun. 20, 1996
Applicant:
Inventors:

Nitin Khurana, Santa Clara, CA (US);

Ted Guo, Palo Alto, CA (US);

Assignee:

Applied Materials, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ; H01L / ;
U.S. Cl.
CPC ...
438627 ; 438640 ; 438653 ; 438714 ; 438906 ;
Abstract

A process for fabricating electronic devices which includes the steps of providing a structure that includes a substrate with an overlying dielectric layer having one or more contact holes and/or vias formed therein; depositing a barrier layer over the structure so that the barrier layer penetrates into the contact holes and/or vias; plasma etching the deposited barrier layer so as to modify its surface morphology; and after modifying the surface morphology of the deposited barrier layer, depositing a metalization layer over the barrier layer. A two-step preclean to facet upper corners of the holes and/or vias and to clean bottoms of the holes and/or vias is performed prior to the deposition of the barrier layer.


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