The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 21, 1999
Filed:
Dec. 02, 1996
Yoshikazu Ohno, Hyogo, JP;
Mitsubishi Denki Kabushiki Kaisha, Tokyo, JP;
Abstract
A first interlayer insulating layer is formed on a main surface of a substrate. A semiconductor layer is formed on the first interlayer insulating layer. A gate electrode (word line) of a switch MOS transistor is formed under the semiconductor layer. A bit line and a capacitor are formed on the semiconductor layer. The semiconductor layer has a substantially flat upper surface, and an interlayer insulating layer and a second interlayer insulating layer having substantially flat upper surfaces are formed on the semiconductor layer. A capacitor is formed on the second interlayer insulating layer, and the capacitor and the second interlayer insulating layer are covered with a third interlayer insulating layer. Thereby, a level difference between a memory cell array and a peripheral circuitry can be reduced in a semiconductor memory device.