Methodology for designing an integrated circuit using a reduced cell

Abstract

A reduced cell library includes substantially fewer cells than a complete cell library used to finalize the integrated circuit design. Having fewer cells reduces the number of options available to the synthesis tool for realizing a particular RTL description. Hence, the amount of time elapsing during a synthesis run using the reduced cell library may be substantially shorter than a corresponding synthesis run using a complete cell library. The reduced cell library can be used to evaluate the RTL description of an integrated circuit without incurring long synthesis delays. Large problems in the RTL description (with respect to one or more design goals) may be detected, and the RTL description may be modified to correct the problems. Once the RTL description of the integrated circuit substantially meets the design goals of the integrated circuit using the reduced cell library, synthesis using the complete cell library is initiated. The reduced cell library may be used to evaluate alternative RTL descriptions as well as cells proposed for addition into the complete cell library. The reduced cell library can be created even when the complete cell library is not yet available. In one embodiment, each of the cells in the reduced cell library is characterized by a uniform drive strength employed by all cells in the library. Attributes for the cells are generated using design goals, constraints, and assumptions.