The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 21, 1999

Filed:

Nov. 25, 1996
Applicant:
Inventors:

Gregory L Ranson, Ft Collins, CO (US);

Gregg B Lesartre, Ft Collins, CO (US);

Russell C Brockmann, Ft Collins, CO (US);

Douglas B Hunt, Ft Collins, CO (US);

Steven T Mangelsdorf, Ft Collins, CO (US);

Assignee:

Hewlett-Packard Company, Palo Alto, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
39518306 ;
Abstract

Method of processing information in a microprocessor. At a first time during the life cycle of an instruction, a first set of microprocessor self-monitoring information is generated. The first set of mnicroprocessor self-monitoring information is stored, information necessary to execute the instruction is stored, and the two are associated. At a second time during the life cycle of the instruction, a second set of microprocessor self-monitoring information may be generated. This is also stored and is associated with the information necessary to execute the instruction. If the instruction retires, the first and second information may be retrieved for use in microprocessor testing. The information may also be used as soon as it is generated, for example by communicating the information itself or indicators derived from it to a state machine configured to facilitate microprocessor testing. The invention may also include a method of processing information in a microprocessor to facilitate microprocessor testing operations, wherein system bus monitoring information is generated whenever system bus accesses occur. This information, or indicators derived from it, is communicated to a microprocessor testing state machine on-chip with the microprocessor. In yet other embodiments, the invention may include the steps of: generating microprocessor self-monitoring information at various times during the life cycle of an instruction; utilizing the microprocessor self-monitoring information both when it becomes available as well as later, after retirement of the associated instruction; generating system bus monitoring information whenever system bus accesses occur; and utilizing the system bus monitoring information when it becomes available.


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