The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 21, 1999
Filed:
Oct. 31, 1996
Gregory L Ranson, Fort Collins, CO (US);
Russell C Brockmann, Fort Collins, CO (US);
Robert E Naas, Fort Collins, CO (US);
Hewlett Packard Company, Palo Alto, CA (US);
Abstract
Method for detecting when first and second signal patterns have occurred on a split-transaction bus having transaction identifying indicia: Signal patterns occurring on the bus are compared with a first stored signal pattern. If a match is detected, the transaction identifying indicia that were associated on the bus with the first signal pattern are stored, and a first detection signal is asserted and held asserted. Signal patterns on the bus are then compared with a second stored signal pattern, and transaction identifying indicia occurring on the bus are compared with the indicia previously stored. A match signal is asserted when the first detection signal is asserted and, simultaneously, matches are detected for both of the second signal pattern comparison and the transaction identifying indicia comparison. Circuitry for implementing the method: First comparison circuitry asserts a first detection signal when a first signal pattern is detected on the bus. First storage circuitry stores a record of the first detection signal having been asserted. Second storage circuitry stores the transaction identifying indicia present on the bus when the first signal pattern is detected. Second comparison circuitry compares the signal patterns on the bus with a stored signal pattern, and third comparison circuitry compares the transaction identifying indicia present on the bus with the indicia stored in the second storage circuitry. When the second and third comparison circuitries simultaneously indicate matches and the first storage circuitry indicates that the first signal pattern was previously detected, output generation circuitry asserts a match signal.