The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 21, 1999

Filed:

Oct. 29, 1997
Applicant:
Inventor:

Kouichi Morikawa, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C / ;
U.S. Cl.
CPC ...
36523005 ; 36518905 ; 36523008 ;
Abstract

The present invention provides a semiconductor memory capable of improving a write address generator which performs complained control by using many gates and capable of reducing layout area. A FIFO semiconductor memory having plural input ports is provided with a memory array MARRAY of m-word.times.n bit.times.2-having 1W1R cell, a write address generator WAG consisted of a shift register, a valid bit VB of m-word.times.2-bit having 1W1R cell, a write buffer WDBV for the valid bit, a valid bit sense amplifier SAV, a read control RCTL judging validness of read data and a read address generator having a circuit controlling update of read address.


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Morikawa, Kouichi. (1999). Semiconductor memory (U.S. Patent No. 5956287). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5956287

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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