Methods and apparatus for the efficient implementation of signal

Abstract

Methods and apparatus for performing packet synchronization recovery and error detection operation on packets including a CRC check byte, e.g., MCNS packets, are described. The present invention uses a memory during a sync acquisition mode of operation to serve as a storage device for the output of a first function circuit. The delayed bits are used as the input along with current bits from the packet stream to a second function circuit. The second function circuit generates a syndrome byte of interest. When the received packets are error free and the decoder is properly aligned with the packet structure of the bitstream, the syndrome byte of interest will assume a preselected value, e.g., 47 Hex. Once packet synchronization has been achieved, the relatively few bits output by the first function circuit which are required as delayed inputs to the second function circuit are identified and stored using a delay register which is much smaller than the memory. By switching to the delay register, the memory previously used for feedback purposes is rendered available for use during sync lock mode for other purposes. Thus, the memory can be re-used as a packet data delay memory during sync lock mode operation. In such an embodiment, received packet data is delayed one packet time period so that the generated syndrome byte corresponding to the delayed packet data can be inserted into the packet stream as the first byte of a transport data packet thereby providing an error indicator signal at the start of a packet.