Method and apparatus for synchronizing digital speech communications

Abstract

A digital speech communication system having improved synchronization. The present digital speech communication system reduces the unit of degradation to a single speech sample, rather than a multi-sample frame, while maintaining the bit rate efficiency of the DSVD system and other systems where speech is encoded into large blocks and is subject to variable delay and mismatched clocks. The basic unit that is dropped or artificially inserted by the receiver, if the buffer overflows or empties, respectively, is reduced to a single speech sample. The speech frames produced by the demultiplexer are written into a frame buffer, in units of frames, at a rate determined by the clock signal, S2, that is extracted from the received signal by a timing recovery function in the modem. In accordance with the present invention, the frames are read out of the buffer into the decoder using the same extracted clock signal, S2. In this manner, once the buffer is partially full, the frame buffer will not overflow or empty. The speech decoder converts the coded speech into blocks of speech samples. The blocks of speech samples are then written to a variable frame buffer, in accordance with the extracted clock signal, S2. The variable frame buffer is allowed to partially fill, before the speech samples are read out to the digital-to-analog converter according to a clock signal, S3, at the 8 kHz sample rate, for presentation to the listener. When the variable frame buffer overflows, only a single speech sample needs to be discarded rather than an entire frame of multiple samples. Likewise, when the variable frame buffer empties, only a single extraneous speech sample need be inserted. The number of samples in the variable frame buffer will preferably be kept within predefined tolerances by a write process and a read process.