Method of fabricating non volatile memory device with memory cells which

Abstract

According to the present invention, there is provided a non-volatile semiconductor memory device including a memory cell array in which a plurality of memory cells are arranged, wherein the memory cells contain two or more types of memory cells, which differs in gate couple ratio. Each memory cell includes source-drain regions provided apart from each other in a semiconductor substrate having a conductivity type, the source-drain regions having a conductivity type opposite to that of the semiconductor substrate, a floating gate provided above a channel region formed between the source-drain regions, and a control gate provided above a surface of the floating gate, and the memory cells contain two or more types of memory cells, which differ in relation to an area of a region in which the floating gate and the control gate overlap. The memory cells having a low gate couple ratio exhibit characteristics similar to those of a mask ROM, which gives priority to reading, whereas the memory cells having a high gate couple ratio, exhibit excellent programming and erasing characteristics.