Semiconductor memory device capable of page mode or serial access mode

Abstract

A semiconductor memory is arranged so that a first memory cell array is provided on one side of a set of a row decoder and word line driving circuits, while a second memory cell array is provided on an opposite side thereof. In the semiconductor memory thus arranged, the first memory cell array has less memory cells so that the first memory cell array has shorter word lines, so that more speedy access to a top data is achieved. By doing so, the access to the top address is made speedy in the high access mode such as the page mode or the serial access mode, with no increase in chip areas in the semiconductor memory and no increase in power consumption. Furthermore, in a semiconductor memory which stores first data requiring a comparatively higher read-out speed (for example, program data) and second data requiring a read-out speed lower than that of the first data, the first data is stored in the memory cell array having the shorter word lines, while the second data is stored in the memory cell array having the longer word lines. By doing so, read-out speeds in accordance with the types of stored data can be obtained, without wasteful power consumption in the word line driving circuits.