The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 14, 1999

Filed:

Dec. 16, 1996
Applicant:
Inventor:

Yuichi Oshino, Tokyo, JP;

Assignee:

Kabushiki Kaisha Toshiba, Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ; H01L / ;
U.S. Cl.
CPC ...
257156 ; 257155 ; 257147 ; 257341 ;
Abstract

A semiconductor device has a low lifetime layer in a selective portion of an N-type drain region to prevent a change in the element characteristic due to Fe contaminants, even if the device is kept at a high temperature. An impurity of a concentration of at least 10.sup.16 atoms/cm.sup.3 is deposited on a first main surface of the N-type drain region, and diffused into the region to a depth of 10 .mu.m, thereby forming a P-type anode region. An anode metal electrode is formed on the surface of the anode region. A P-type base region and an N-type source region are formed in a second main surface of the N-type drain region by ion injection or the like. A gate electrode is formed above the second main surface with a gate oxide film interposed therebetween. A metal gate electrode is formed in contact with the gate electrode. A source metal electrode is formed on the source region and the base region so as to short-circuit them. The low lifetime layer is formed in a selective portion of the N-type drain region.


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