The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 14, 1999

Filed:

Dec. 19, 1997
Applicant:
Inventors:

Kazuhiro Yuuki, Kawasaki, JP;

Yukihiro Katsumata, Kawasaki, JP;

Takeo Tabata, Kawasaki, JP;

Shinichiro Nakamura, Unoke-machi, JP;

Assignees:

Fujitsu Limited, Kawasaki, JP;

PFU Limited, Kahoku, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F / ; G06F / ;
U.S. Cl.
CPC ...
713-1 ; 709208 ; 709209 ; 712 31 ; 714 13 ;
Abstract

One of processors connected effectively to a system is allocated to a master processor and the other remaining processors are allocated to slave processors. Each processor compares the self processor number of a processor number register and the processor number of the other processor of a processor effective register. For example, when the self processor number is smallest as compared with the other processor numbers, it is recognized that the self processor is a master processor. A master initialization diagnosing process after completion of the allocation is monitored by the slave processor. When an abnormality of the master processor is recognized, a degeneration to disconnect the master processor from the system is executed and is again reconstructed by the allocating process of master/slaves. Even when an abnormality occurs in the master processor, the operation in which the system was degenerated can be executed until the minimum construction in which two or more processors normally operate.


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