The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 14, 1999
Filed:
Jan. 10, 1997
Applicant:
Inventor:
Jianwei Liu, Manchester, GB;
Assignee:
ARM Limited, Cambridge, GB;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
708700 ;
Abstract
A binary adder circuit includes carry evaluation circuits that encode a carry production control signal using two signal values (V, W) such that V=W=0 indicates a carry kill, V=W=1 indicates a carry generate and V.noteq.W indicates a carry propagate. The carry evaluation circuit may be implemented in static or dynamic CMOS logic.
Liu, Jianwei. (1999). Digital adder circuit (U.S. Patent No. 5951630). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5951630
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile