The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 07, 1999
Filed:
Feb. 03, 1997
William W Lee, Palo Alto, CA (US);
Industrial Technology Research Institute, Hsinchu, TW;
Abstract
A method for making air-insulated planar metal interconnections having low interlevel capacitance with improved RC time delays for integrated circuits is achieved. The method involves using a multilayer of negative and positive photoresists in which open regions are developed in the negative photoresist for the metal interconnections, and open regions are developed in the positive photoresist for via holes. The open regions are then filled with a Ti/TiN diffusion barrier deposited at room temperature and an electroless plated copper, and polished back using a Dual Damazene to form the interconnecting metal level and the via hole stud. The method is repeated several times to form multilevel metal interconnections. The remaining photoresist is then totally removed by oxygen ashing to leave a free-standing multilevel metal interconnection structure that is conformally coated with a thin Al.sub.2 O.sub.3 passivation layer and having air insulation. This results in a much lower inter- and intralevel capacitance and improved circuit performance.