The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 07, 1999
Filed:
Mar. 31, 1998
Stephen A Dahl, Rochester, MN (US);
John C Endicott, Rochester, MN (US);
Peter J Heyrman, Rochester, MN (US);
R Karl Kirkman, Rochester, MN (US);
Richard G Mustain, Rochester, MN (US);
Jon H Peterson, Rochester, MN (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method and data processing system for emulating a program are disclosed. According to the present invention, the data processing system runs under a first operating system and emulates the execution of a program under a second operating system within a second data processing system. The data processing system includes a memory which stores at least a portion of the first operating system and an emulator comprising a plurality of routines which each emulate an instruction utilized by the first operating system. The memory further includes a simulated mass storage data area which stores at least a portion of the program and a simulated main memory data area. The data processing system further includes a processor which executes instructions within the program under the first operating system by emulation. According to the present invention, the emulator accesses instructions of the program directly from the simulated mass storage data area to minimize emulation overhead. According to a second aspect of the present invention, the data processing system further includes a cache memory comprising a number of cache lines. The routines are stored within main memory such that when the routines are mapped into the cache, a first instruction within each of the emulation routines is aligned with a different one of the cache lines. According to a third aspect of the present invention, when executing instructions within a routine of a first emulated instruction, the processor prefetches a second emulated instruction prior to completion of the first emulated instruction.