The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 07, 1999

Filed:

Dec. 01, 1997
Applicant:
Inventor:

Shigeaki Fujitaka, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
395500 ;
Abstract

An emulator system capable of solving a problem of a conventional emulator system in that it requires a gate array for executing a port function of a peripheral emulation chip because external pins of the peripheral emulation chip cannot achieve the port function required in a peripheral emulation mode. The present emulator system has at least two peripheral emulation chips. Each peripheral emulation chip includes a core block for controlling buses, a peripheral function block for achieving functions of a peripheral device, a mode setting circuit for setting a normal mode enabling the core block or the peripheral emulation mode enabling the peripheral function block, external pins, and a link switching circuit for selecting one of the connections of the external pins with the buses and with the peripheral function block.


Find Patent Forward Citations

Fujitaka, Shigeaki. (1999). Emulator system (U.S. Patent No. 5949984). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5949984

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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