The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 07, 1999
Filed:
Jul. 21, 1997
Oki Electric Industry Co., Ltd., Tokyo, JP;
Abstract
A sense circuit for a DRAM circuit in which small potential difference between bit lines and is produced when the memory cell in the memory cell array is connected to one of the bit lines. The sense circuit starts sensing and amplifying when the sense starting signal changes to 'L' level. An inverter provides a sense activating signal of 'H' level to an NMOS device, while another inverter provides a sense activating signal of 'L' level to a PMOS device. Sense amplifiers 33 are then activated and the potential difference between the bit lines and is amplified. Since the 'L' level of the sense activating signal that is generated by the inverter is set to a value midway between a first power potential VSS and a second power potential VCC, the conductive resistance of the PMOS device is higher than that of a conventional circuit supplied with the first power potential VSS. Consequently, the voltage drop due to the PMOS device increases and power noise is reduced.