Data output related circuit which is suitable for semiconductor memory

Abstract

A high-speed data output related circuit for a memory device reduces the operational cycle time by self-latching data in a data output buffer and self-resetting a main sense amplifier and level shifter, thereby the need for external control signals. A data output related circuit in accordance with the present invention includes: a sense amplifier for generating sensed data; a level shifter for converting the level of the sensed data, thereby generating level shifted data; a data output buffer for self-latching the level shifted data in first latch nodes in response to the level shifted data, for latching the level shifted data latched in the first latch nodes in second latch nodes when a data passing clock is received, and for transmitting data latched in the second latch nodes through output terminals in response to an output enable signal; and a controller for sequentially activating, before the level shifted data arc generated, the operations of the sense amplifier and the level shifter by generating a main sensing enable signal and a shifting enable signal as first and second logic levels in response to a sensing enable signal supplied from the device, and for sequentially disabling, immediately after the level shifted data are self-latched, the operations of the sense amplifier and the level shifter by generating the main sensing enable signal and the shifting enable signal as second and first logic levels, thereby causing the data output buffer to be self-reset when the level shifted data are latched in the first latch nodes.