The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 07, 1999
Filed:
Apr. 25, 1997
Ekanayake A Amerasekera, Plano, TX (US);
Sridhar Ramaswamy, Champaign, IL (US);
Jerold A Seitchik, Dallas, TX (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
An embodiment of the instant invention is a method of optimizing an I/O circuit formed on a substrate with regards to an overvoltage or ESD event wherein the I/O circuit comprises at least one MOS device which has I-V characteristics, the method comprising the steps of: extracting selective electrical characteristics of the MOS device while the MOS device is operating in the avalanche and snapback regions of the I-V characteristics of the MOS device; characterizing the MOS device for the overvoltage or ESD event based on the electrical characteristics of the MOS device under standard operating conditions, the MOS device being comprised of a parasitic bipolar transistor and the substrate having a resistance; and wherein the I/O circuit is optimized for the overvoltage or ESD events by modifying the I/O circuit based on the electrical characteristics of the MOS device in conjunction with the characterization of the parasitic bipolar transistor and the substrate resistance.