Schematic design entry with annotated timing

Abstract

The invention provides to the user a way of ascertaining the estimated delay through a circuit, by placing a timing attribute on the schematic symbol for the circuit that automatically displays the estimated delay. Reported delays may include maximum delay, typical delay, and/or minimum delay on the critical path. In a first embodiment, the schematic entry software consults a macro speeds file to obtain delay information for the macro. In a second embodiment, the macro delay information is added to the standard device speeds file. In a third embodiment, the symbol file (or other file) for the macro includes a formula for the critical path delay through the macro, based on the delays in the standard device speeds file. The schematic entry software therefore uses the standard device speeds file to calculate the macro delay. According to a second aspect of the invention, schematic-entry software accepts pointer-driven (e.g., mouse-driven) input designating starting and ending points on a path, and reports the path delay between these points. According to a third aspect of the invention, schematic-entry software accepts pointer-driven input designating a group of schematic symbols and reports the path delay on the critical paths through the circuit comprising the designated symbols.