Nominal temperature and process compensating bias circuit

Abstract

The present invention provides a nominal temperature and process compensating bias circuit for an integrated circuit. The bias circuit comprises a current source, a pair of linear devices, and a current stage. The current source generates a bias current. The pair of linear devices includes a first linear device and a second linear device. The first and second linear devices are coupled to each other and to the current source at a common node to enable the bias current from the current source to flow through the linear devices. The current stage includes a first transistor and a second transistor with the first transistor being coupled to the first linear device at the drain node of the first transistor and the second transistor being coupled to the second linear device at the drain node of the second transistor. In this configuration, the first and the second transistors have different channel width (W) to channel length (L) ratios such that the transistor with a larger W to L ratio conducts more current than the transistor with smaller W to L ratio to generate a voltage at the drain of the transistor with larger W to L ratio, thereby counteracting variations in temperature and process in the integrated circuit.