Enhanced flip-flop for dynamic circuits

Abstract

A flip-flop with enhanced support for dynamic circuits. The flip-flop comprises at least one data input node along with at least one inverting and at least one non-inverting output node. A clock input node receives an external clock signal and transmits it to a clocking unit which, in turn, generates a clock signal therefrom for gating an input signal received at the data input node. A storage unit holds the input signal value upon assertion of the clock signal and simultaneously transmits that value in appropriate logic level to inverting and non-inverting outputs. It is understood that the inverting and non-inverting outputs represent complementary signal values as is normally known in the art. The flip-flop further comprises a clear input node which is coupled to an edge-sensitive quiescent state control unit. A predetermined logic state transition, i.e. high to low or low to high, of a control signal applied to the clear input node triggers the edge-sensitive quiescent state control unit which, in turn, drives the inverting and non-inverting nodes to an identical logic level, i.e. either quiescent high or quiescent low depending on the design considerations. A non-inverted output signal and/or an inverted output signal at the inverting and non-inverting nodes, respectively, may be used to control the discharge of a node in a dynamic circuit. Since each of the output signals is cleared to a quiescent state after the signal is applied as an input to the dynamic circuit, the output of the flip-flop will not erroneously cause discharge of the node of the dynamic circuit when the next edge of the clock signal occurs.