The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 07, 1999
Filed:
Dec. 29, 1998
Tetsuji Ichiki, Hamamatsu, JP;
Yamaha Corporation, Hamamatsu, JP;
Abstract
A tone generator chip is formed of a semiconductor substrate and is configurable under different operation modes in combination with memories accessible via external buses for generating a tone by using the memories. In the tone generator chip, a sound source block is controllable for generating a tone and includes a reading circuit for reading waveform data to generate the tone and a digital signal processing circuit for processing the waveform data to impart an effect to the tone. A central processing unit is integrated in the semiconductor substrate together with the sound source block for controlling the sound source block. A first access manager manages an access status from each of the reading circuit, the digital signal processing circuit and the central processing unit to a first external bus for access to a memory. A second access manager manages an access status from each of the reading circuit, the digital signal processing circuit and the central processing unit to a second external bus provided separately from the first external bus for access to another memory. A mode control designates a specific one of the different operation modes to enable the first access manager and the second access manager to set the respective access statuses, thereby configuring the reading circuit, the digital signal processing circuit and the central processing unit according to the specific operation mode in combination with the memories configured corresponding to the specific operation mode.