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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 5946710 B1

PDFFull Text
Date of Patent:
Aug. 31, 1999

Filed:

Nov. 14, 1996

Selectable two-way, four-way double cache interleave scheme

Applicant:
Inventors:

Mitchell A Bauman, Circle Pines, MN (US);

Donald C Englin, Shoreview, MN (US);

Assignee:

Unisys Corporation, Blue Bell, PA (US);

Attorneys:

Johnson; Charles A.

Starr; Mark T.

Primary Examiner:

Eddie P Chan

Assistant Examiner:

Gary J Portka

Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
711129 ; 711130 ; 711153 ;
Abstract

Method and apparatus for maximizing cache memory throughput in a system where a plurality of requesters may contend for access to a same memory simultaneously. The memory utilizes an interleaved addressing scheme wherein each memory segment is associated with a separate queuing structure and the memory is mapped noncontiguously within the same segment so that all segments are accessed equally. Throughput is maximized as the plurality of requesters are queued evenly throughout the system.

Find Patent Forward Citations

Bauman, Mitchell. (1999). Selectable two-way, four-way double cache interleave scheme (U.S. Patent No. 5946710). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5946710

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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