The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 31, 1999
Filed:
Oct. 14, 1997
Michio Miura, Hamamatsu, JP;
Kenzaburou Iijima, Hamamatsu, JP;
Yamaha Corporation, , JP;
Abstract
A semiconductor chip mounting method consisting of steps is performed to mount a semiconductor chip on a substrate. Herein, an electrode is formed on a main surface of the semiconductor chip and is covered with an insulating film. A contact hole is formed through the insulating film to be in contact with a part of the electrode. In addition, a Ni layer is formed to cover the contact hole. A wiring layer is formed on a main surface of the substrate and is covered with an insulating film. To achieve laser beam bonding effected between the semiconductor chip and substrate, a solder is provided for either the semiconductor chip or the substrate. For example, it is possible to provide a solder layer which is formed through a part of the insulating film to be in contact with the wiring layer of the substrate; or it is possible to provide a solder bump which projects from a concavity of the Ni layer of the semiconductor chip. Next, a laser beam is irradiated through the substrate, having laser beam permeability, and toward the solder. Thus, the semiconductor chip is bonded together with the substrate. Incidentally, a diameter in irradiation of the laser beam can be narrowed within a range between 1 .mu.m and 25 .mu.m, for example. This brings a reduction in a contact area between the semiconductor chip and substrate which are bonded together. Results of our studies show that a good electric connection can be provided between the electrode of the semiconductor chip and the wiring layer of the substrate under a limited condition where the Ni layer and the wiring layer both have a thickness which ranges between 0.6 .mu.m and 3 .mu.m, for example.