The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 31, 1999

Filed:

Aug. 14, 1997
Applicant:
Inventor:

Mamoru Ishikiriyama, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
438459 ; 438406 ;
Abstract

In a method for manufacturing a dielectric isolation substrate according to the present invention, during the process of pressing a semiconductor substrate (wafer), a dummy chip 103 is positioned toward the outside edge of the wafer with respect to the LSI chip 102, which is pressed into contact last, V-grooves 103A in the dummy chip 103 are formed to be deeper than V-grooves 102A in the LSI chip 102 so that voids can be effectively pushed into the dummy chip 103. Consequently, isolation of the LSI chip caused by voids can be prevented, thereby achieving an improvement in yield.


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Ishikiriyama, Mamoru. (1999). Method for manufacturing a dielectric isolation substrate (U.S. Patent No. 5946584). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5946584

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