The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 31, 1999
Filed:
Aug. 28, 1996
Soichi Ito, Tokyo, JP;
NEC Corporation, Tokyo, JP;
Abstract
In an automatic positioning/wiring method for a flip-chip semiconductor device which is adapted to design a semiconductor chip including test pads used for inputting/outputting signals in a test, chip terminals respectively arranged on or near the test pads to serve as input/output terminals for an external unit, input/output buffers for exchanging signals with the external unit, and internal circuit blocks which perform predetermined circuit operations in response to signals from the input/output buffers, the internal circuit blocks and the input/output buffers are position/wired in arbitrary regions on the semiconductor chip in an automatic positioning/wiring design process on the basis of a result of a layout position determination process for performing definition such that the input/output buffers and the internal circuit blocks are arranged without discrimination layout regions thereof. A floor plan formation process is performed to arrange the input/output buffers into predetermined groups within the arbitrary region in the form of rows each parallel to one of sides of the semiconductor chip.