Synchronous semiconductor memory device capable of reducing delay time

Abstract

In a synchronous dynamic random access memory (SDRAM), one bank A is divided into banks A0 and A1, and two sets of writing-related circuits are arranged corresponding to each memory cell array bank and are capable of performing writing operation substantially independently. The first and second bits of write data applied successively from the outside world are applied alternately to write registers. Since the I/O line pair is connected to the selected memory cells in respective memory cell array banks after incorporation of the second bit data to be written is completed, the potential levels of the corresponding I/O line pair always change to the corresponding potential levels from the initial state in writing the first and second bit data.