The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 31, 1999
Filed:
Dec. 23, 1997
Kiyoshi Nishimura, Kyoto, JP;
Rohm Co., Ltd., Kyoto, JP;
Abstract
It is an object of the present invention to provide a ferroelectric memory device having a high integration and capable of maintaining nonvolatility. A threshold voltage V.sub.th of a ferroelectric memory element is set at value slightly higher than a voltage -V.sub.1. A voltage 0V is applied as a gate voltage V.sub.G when the stored data is read out. A voltage V.sub.1 is generated at a MOS capacitor C.sub.MOS if the data 'High' is stored and the voltage -V.sub.1 is generated at the MOS capacitor C.sub.MOS if the data 'Low' is stored. The stored data is read out by detecting a drain current during generation of the voltages. Also, a voltage 0V is applied as the gate voltage V.sub.G when stand-by operation is carried out. In this way, variation of the gate voltage V.sub.G caused by switching ON and OFF of a power source can be prevented. So that, nonvolatility of the ferroelectric memory device can be maintained as a result of preventing spontaneous polarization of a ferroelectric capacitor C.sub.ferro. Further, it is not necessary to provide a circuit for generating a voltage for using read out the data to the ferroelectric memory device. So that, integration of the ferroelectric memory device can be increased.