The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 31, 1999

Filed:

Apr. 23, 1998
Applicant:
Inventors:

Hsiao-Ping Lin, Taipei, TW;

Tin-Hao Lin, Hsinchu, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
257203 ; 257207 ;
Abstract

A silicon chip having a mixed input/output slot structure comprising a core region having a plurality of circuits formed thereon, a wiring region surrounding and linked to the core region, and an input/output area surrounding and linked to the wiring region, where the input/output area has a plurality of input/output slots and four corner cells. The input/output slots can be divided into groups with each group having a different height, and input/output slots on the same side of the input/output area all have the same height. Therefore, a choice of sides for placing the input/output slots can be made, and the layout of input/output slots around the silicon chip is not be restricted by one side. Hence, chip size can be reduced and chip surface can be fully utilized.


Find Patent Forward Citations

Lin, Hsiao-Ping. (1999). Silicon chip having mixed input/output slot structure (U.S. Patent No. 5945696). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5945696

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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