Interrupt routing circuits, systems and methods

Abstract

A computer system including an arrangement for programmably assigning interrupts to a larger set of interrupt channels. The computer system includes a microprocessing unit ('MPU' 102), a peripheral processing unit ('PPU' 110) that communicates with the MPU and a peripheral control unit ('PCU' 112) capable of communicating with the PPU and with at least one associated peripheral device. The PCU has associated therewith a first number, m, of interrupts for signalling to the MPU. The MPU has a second number, n, of interrupt channels over which interrupts are communicable to said MPU. A first register (IN1616) is provided in the PCU for storing a routing value representing the assignment of the m interrupts of the PCU to a selected subset of m channels of the n interrupt channels. A second register (IN1222) is provided in the PPU for storing the routing value. A number, m, connections are provided between the PCU and the PPU for transmitting the m interrupts from the PCU to the PPU. Finally, a logic unit (3820, 3830, 914) is provided that is responsive to the receipt of an interrupt on one of the m connections and to the stored routing value in the second register for communicating an interrupt to the MPU and for identifying to the MPU the m selected interrupt channels to which the communicated interrupt is assigned. Other devices, systems and methods are also disclosed.