The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 24, 1999

Filed:

Nov. 18, 1996
Applicant:
Inventors:

Shao-Kun Jiang, San Diego, CA (US);

Le T Nguyen, Monte Sereno, CA (US);

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
36478701 ; 36478601 ; 36478602 ; 36478603 ; 36478604 ; 36478702 ; 36478703 ; 36478704 ; 364749 ;
Abstract

An adder circuit includes various methods to control the carry bit at data boundaries when attempting to process multiple data of multiple types. One method is to generate both propagate and generate signals from the input data and modified propagate and generate signals from the data boundaries, which can then be used in a conventional carry-lookahead adder to produce a resulting sum that is correct regardless of the data type being processed. Another method is to insert special carry blocking, propagating or generating cells at the data boundaries of the input data. These cells are then filled with the appropriate blocking, propagating or generating signals, either by table look-up or circuit implementation using data type and processing type inputs. This data stream can then be added with a conventional adder. However, if the special cell replaces data at the boundaries, another adder can be used to process this boundary data separately prior to inserting the special cell. Instead of using another adder, the data stream may be expanded such that the special cell does not replace any data at the boundaries. The expanded data stream is then processed with a conventional adder capable of handling the expanded width.


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