Digital circuit for conserving static current in an electronic device

Abstract

This invention relates to a digital circuit for controlling the power usage of an electronic device such as a read only memory (ROM) for a computer device, particularly a portable computer device that relies on a battery power source. The circuit includes the latch, a positive edge detecting circuit, a negative edge detecting circuit, a guaranteed reset circuit, and a delay circuit. Control signals from the device open and close the latch when either a rising or falling edge of these control signals is detected by the edge detecting circuits. The latch itself includes a three input NAND gate and a two input NAND gate. The guaranteed reset circuit ensures that the circuit is initiated. The delay circuit includes a series of inverters and loads. The edge detecting circuits generate a pulse when a rising or falling edge is detected, and include a pulse generating portion, a NAND gate and inverters.