Method and apparatus for dram refresh using master, slave and

Abstract

Method and apparatus for refreshing DRAM devices (chips) in a computer system. Each DRAM device incorporates circuitry to carry out a burst of RAS cycles during each refresh period. Three different modes are used to trigger the device into refresh. In one mode, each DRAM device incorporates a refresh timer; only one master DRAM device in the system has its refresh timer enabled. The refresh master device generates a refresh request every time the refresh timer times up. A memory controller, after receiving the request, generates an acknowledge signal when certain system conditions are met. All DRAM devices in the system monitor the refresh request and acknowledge handshake continuously. Upon detection of refresh acknowledge, each DRAM device caries out a sequence of predesignated refresh cycles. In a second mode, the DRAM devices are all strapped as refresh slaves and the refresh timer resides in the memory controller which drives the same refresh acknowledge signal low for two clock cycles when the refresh timer times-up. Upon receiving the acknowledge signal, the DRAM devices each carry out the refresh operation. In a third (self refresh) mode, each DRAM device generates a internal clock signal, which has a different frequency and phase relationship with the external clock signal, for operating its internal refresh timer and refresh logic. Each DRAM device carries out its refresh periodically without communicating to the controller or the other DRAM devices. Each of the three refresh modes is selected by externally supplied mode select signals.