The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 17, 1999
Filed:
Feb. 09, 1998
Applicant:
Inventors:
Atul V Ghia, San Jose, CA (US);
Suresh M Menon, Sunnyvale, CA (US);
Assignee:
DynaChip Corporation, Sunnyvale, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
395555 ; 395559 ; 711100 ;
Abstract
A duty cycle controller for generating proper control signals for an SRAM in an FPGA in the proper sequence and spaced at the proper times to guarantee proper operation of the SRAM regardless of the frequency of duty cycle of the clock selected by the user to synchronize and drive operations of the SRAM.
Ghia, Atul. (1999). Duty cycle controller for clock signal to synchronous sram on fpga (U.S. Patent No. 5940606). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5940606
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile