The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 17, 1999
Filed:
Oct. 30, 1996
Takayuki Takano, Yokohama, JP;
Susumu Nitta, Yokohama, JP;
Kabushiki Kaisha Toshiba, Kawasaki, JP;
Abstract
A logic circuit has a first circuit block, a second circuit block, and a test circuit composed of a first multiplexer and a second multiplexer. In normal operation mode, the first multiplexer connects the output terminal of the first circuit block to the input terminal of the second circuit block on the basis of the first test signal, and the second multiplexer disconnects the input terminal of the second circuit block from the external output terminal on the basis of the second test signal; in a first test mode for outputting a signal outputted by the first circuit block through the external output terminal, the first multiplexer connects the output terminal of the first circuit block to the input terminal of the second circuit block on the basis of the first test signal, and the second multiplexer connects the input terminal of the second circuit block to the external output terminal on the basis of the second test signal; and in a second test mode for inputting a signal inputted to the second circuit block through the external input terminal, the first multiplexer connects the external input terminal to the input terminal of the second circuit block on the basis of the first test signal, and the second multiplexer disconnects the input terminal of the second circuit block from the external output terminal on the basis of the second test signal. Therefore, the test circuit can inspect whether there exists any erroneous connection relationship in the normal operation mode of the logic circuit, after the test circuit has been connected.