The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 17, 1999
Filed:
Apr. 30, 1997
Tuan Q Dao, Richardson, TX (US);
Rekha Suryanarayana, Plano, TX (US);
Naoki Hayashi, Dallas, TX (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
A microprocessor (5) having an on-chip floating-point unit, or FPU, (31) is disclosed. Snoop logic (37) is present in the integer pipeline to detect the presence of floating-point load instructions, in which floating-point operands are retrieved from system main memory or from on-chip cache memory (6, 16.sub.d, 18) by load/store units 40. For such operations in which the floating-point operands are of single precision or double precision, immediate formatter (70) receives the retrieved operands on load/store buses (LOAD.sub.-- DATA0, LOAD.sub.-- DATA1) and reformats the operands into a higher precision format for use internally by FPU (31). Rebias circuitry (78) is provided within immediate formatter (70) to change the bias of the exponent portion of the reformatted floating-point operands. Selection of the appropriate operand for application to the execution stages (56, 58, 60) of FPU (31) is made by a multiplexer (74) responsive to control signals (BSEL) derived from load/store directives detected by snoop logic (37). The operation of the immediate formatter (70) enables the reformatting of single precision and double precision floating-point operands within the same machine cycle as their receipt on load/store buses (LOAD.sub.-- DATA0, LOAD.sub.-- DATA1), thus improving performance of microprocessor (5).