The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 17, 1999

Filed:

May. 06, 1997
Applicant:
Inventors:

Hideki Abe, Sapporo, JP;

Noriyuki Iwakura, Sapporo, JP;

Takahisa Hatano, Sapporo, JP;

Yoshikuni Shindo, Sapporo, JP;

Kazuhiro Yamada, Sapporo, JP;

Kazushige Kida, Sapporo, JP;

Kazunari Yamaguchi, Sapporo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04N / ;
U.S. Cl.
CPC ...
348537 ; 348536 ; 348541 ; 348544 ; 348500 ; 345212 ; 345213 ;
Abstract

The invention presents a dot clock reproducing apparatus for automatically reproducing the dot clock easily, by setting the dot clock frequency of a video signal source, and correcting the phase difference of the dot clock occurring in the transmission route or the like, and also presents a dot clock reproducing method comprising, in dot clock reproduction, a step of sampling at a frequency different from the dot clock of video signal, a step of detecting the aliasing frequency component occurring at this time, and a step of reproducing the dot clock so as not to cause this aliasing frequency component, and as an apparatus employing such method, the invention further provides a dot clock reproducing apparatus comprising A/D converting means for receiving an adjusting signal delivered from a video signal source, and sampling this adjusting signal to convert into a digital signal, PLL means for dividing a specified synchronizing signal and generating a sampling clock for the A/D converting means, frequency analyzing means for analyzing the frequency of the adjusting signal from the output of the A/D converting means, and dividing ratio setting means for controlling the dividing ratio of the PLL means from the output of the frequency analyzing means, wherein the dot clock is reproduced so that the output of the PLL means may be used as the dot clock signal, thereby realizing a dot clock reproducing apparatus for reproducing automatically the dot clock easily, by setting the dot clock frequency of the video signal source, and correcting the phase difference of the dot clock occurring in the transmission route or the like.


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