Apparatus for decoding variable length coded data

Abstract

An apparatus for decoding compressed image data which is variable length coded, having a single segment memory. An input data processor counts the effective AC data and generates an address of where to write the AC data. An MR/VR flag write processor counts all of the MR/VR flags existing in one segment synchronous section stored in the segment memory and generates an address of where to write MR/VR flags existing in the respective DCT blocks. An MR/VR flag memory stores the address of where to write the MR/VR flag generated in the MR/VR flag write processor. An MR/VR flag read address generator generates the address of where to read the MR/VR flag stored in the MR/VR flag memory. An AC data read address generator generates the address of where to read the AC data stored in the segment memory with reference to a start absolute address. A run/amplitude buffer latches the run/amplitude data read from the segment memory. An address reducer clears the latched run and amplitude data before the data of the next area is read, and reduces the address increased due to the run and amplitude in the case where the run does not exist and only amplitude data exists in the data read from the segment memory. A DCT block counter counts the DCT blocks in order to determine in which DCT block the MR/VR data latched in the run/amplitude buffer exists.